1. Field of the Invention
The present invention relates to a semiconductor device in which a high-voltage MOS transistor and a peripheral circuit are provided together and to a method for fabricating the same.
2. Description of the Prior Art
FIG. 8A and FIG. 8B show cross sections of a conventional semiconductor device in which a lateral high-voltage MOS transistor and a peripheral circuit are provided together. FIG. 8A is a cross section of a lateral high-voltage MOS transistor region 23, taken along the line a-a of FIG. 9 showing a plan view of a lateral high-voltage MOS transistor of conventional type. FIG. 8B is a cross section taken along the line b-b of FIG. 9. A source electrode, a source contact, a drain electrode, and a drain contact are not shown in FIG. 9.
In the conventional semiconductor device, as shown in the left drawing of FIG. 8A, an N well region 2 exists in a P-type silicon substrate 1 of a P-type MOS region 22. A gate insulating film 3 is provided on each of the P-type silicon substrate 1 and the N well region 2. A gate electrode 4 is provided on the respective gate insulating films 3. N-type source/drain regions 5 exist in the P-type silicon substrate 1 on both sides of the gate electrode 4 of the N-type MOS region 21. P-type source/drain regions 6 exist in the N well region 2 on both sides of the gate electrode 4 of the P-type MOS region 22.
Further, as shown in the right drawing of FIG. 8A, an N-type low concentration drain region 11 and an N-type source region 12, spaced apart from each other, exist in a P-type silicon substrate 1 of a lateral high-voltage MOS transistor region 23. A channel region 13 is provided in the substrate surface between the N-type low concentration drain region 11 and the N-type source region 12. A gate insulating film 3 is provided on the channel region 13, and a gate electrode 4 is provided on the gate insulating film 3. An N-type high concentration drain region 14 exists in the N-type low concentration drain region 11. A P-type substrate contact region 15a is provided under the N-type source region 12 and spaced apart from the gate electrode 4.
The cross section of FIG. 8B taken along the line b-b of FIG. 9 shows that a P-type substrate contact region 15b, spaced apart from the N-type low concentration drain region 11, is provided in the P-type silicon substrate 1.
An interlayer insulating film 30 is provided on the P-type silicon substrate 1 of the N-type MOS region 21, P-type MOS region 22, and lateral high-voltage MOS transistor region 23 as shown in FIG. 8A and FIG. 8B. Part of the interlayer insulating film 30 on the N-type high concentration drain region 14 of the lateral high-voltage MOS transistor region 23 has an opening, in which a drain electrode 16 is formed to connect the N-type high concentration drain region 14 with an external device via the opening. Parts of the interlayer insulating film 30 on the N-type source region 12 and the P-type substrate contact region 15b have openings, too, in each of which a source electrode 17 is formed to connect the N-type source region 12 and the P-type substrate contact region 15b with an external device via the opening. Parts of the interlayer insulating film 30 formed on the source/drain regions of the N-type MOS region 21 and the P-type MOS region 22 have openings, too, and a drain electrode 18 or a source electrode 19 is formed in a corresponding one of the openings.
In the fabrication of the semiconductor device, the N-type source/drain regions 5 of the N-type MOS region 21 and the N-type source region 12 of the lateral high-voltage MOS transistor region 23 are formed in the same step. The P-type source/drain regions 6 of the P-type MOS region 22 and the P-type substrate contact regions 15a and 15b of the lateral high-voltage MOS transistor region 23 are formed in the same step.